AR# 7017

WebPACK - Can I use a VHDL or Verilog source file, or is the tool ABEL-based?

描述

Can I use a VHDL or Verilog source file, or is the tool ABEL-based?

解决方案

WebPACK 10 and earlier supports synthesis in three HDL formats: ABEL, VHDL, and Verilog.  

 

WebPACK 11 and Later supports Verilog and VHDL synthesis.

AR# 7017
日期 05/14/2014
状态 Archive
Type 综合文章