Can I use a VHDL or Verilog source file, or is the tool ABEL-based?
WebPACK 10 and earlier supports synthesis in three HDL formats: ABEL, VHDL, and Verilog.
WebPACK 11 and Later supports Verilog and VHDL synthesis.
AR# 7017 | |
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日期 | 05/14/2014 |
状态 | Archive |
Type | 综合文章 |