This answer record contains the Release Notes and Known Issues for the I2S Receiver and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2018.1 and later.
Modular Media over I2S Receiver Page:
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.
This table correlates the core version to the first Vivado design tools release version in which it was included.
|Core Version||Vivado Tools Version||Change log||IP Patch|
|V1.0 (Rev5)||2020.1||(Xilinx Answer 73626)|
|v1.0 (Rev4)||2019.2||(Xilinx Answer 72923)||(Xilinx Answer 73096)|
|v1.0 (Rev3)||2019.1||(Xilinx Answer 72242)||(Xilinx Answer 73097)|
|v1.0 (Rev2)||2018.3||(Xilinx Answer 71806)|
|v1.0 (Rev1)||2018.2||(Xilinx Answer 71212)|
|v1.0||2018.1||(Xilinx Answer 70699)|
The table below provides Answer Records for general guidance when using the I2S Receiver.
|Article Number||Article Title|
|(Xilinx Answer 73127)||Can I configure a 32-bit data period in the I2S Transmitter/Receiver IP?|
Known and Resolved Issues:
The following table provides known issues for I2S Receiver, starting with v1.0, initially released in Vivado 2018.1.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Article Number||Article Title||Version Found||Version Resolved|
|(Xilinx Answer 73127)||LogiCORE I2S Receiver v1.0 (Rev3) and LogiCORE I2S Transmitter v1.0 (Rev3) - Can I use a 32 bit-data period with the I2S cores?||v1.0(Rev 3)||v1.0(Rev 5)|
|(Xilinx Answer 73124)||LogiCORE I2S Receiver v1.0 (Rev4) and LogiCORE I2S Transmitter v1.0 (Rev4) - Can I use a 32 bit-data period with the I2S cores?||v1.0(Rev 4)||v1.0(Rev 5)|