AR# 70289

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LogiCORE I2S Transmitter - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions

描述

This answer record contains the Release Notes and Known Issues for the I2S Transmitter and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2018.1 and later versions.

Modular Media over I2S Transmitter Page:

https://www.xilinx.com/products/intellectual-property/audio-i2s.html

解决方案

General Information:

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table:

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools VersionIP Change logIP Patch
V1.0 (Rev 5)2020.1(Xilinx Answer 73626) 
V1.0 (Rev 4)2019.2(Xilinx Answer 72923)(Xilinx Answer 73095)
v1.0 (Rev 3)2019.1(Xilinx Answer 72242)(Xilinx Answer 73094)
v1.0 (Rev 2)2018.3(Xilinx Answer 71806) 
v1.0 (Rev 1)2018.2(Xilinx Answer 71212) 
v1.02018.1(Xilinx Answer 70699) 

General Guidance:

The table below provides Answer Records for general guidance when using the I2S Transmitter.

Article NumberArticle Title
(Xilinx Answer 73127)Can I configure a 32-bit data period in the I2S Transmitter/Receiver IP?

Known and Resolved Issues:

The following table provides known issues for I2S Transmitter, starting with v1.0, initially released in Vivado 2018.1.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 73127)LogiCORE I2S Receiver v1.0 (Rev3) and LogiCORE I2S Transmitter v1.0 (Rev3) - Can I use a 32 bit-data period with the I2S cores?v1.0(Rev 3)v1.0(Rev 5)
(Xilinx Answer 73124)LogiCORE I2S Receiver v1.0 (Rev4) and LogiCORE I2S Transmitter v1.0 (Rev4) - Can I use a 32 bit-data period with the I2S cores?v1.0(Rev 4)v1.0(Rev 5)

Revision History:

01/06/2020Added (Xilinx Answer 73127)
12/12/2019Added (Xilinx Answer 73124)

 

  • 11/26/2019 - updated Rev1 ->Rev4
  • 04/04/2018 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
70288 LogiCORE I2S Receiver - Release Notes and Known Issues for the Vivado 2018.1 tool and later versions N/A N/A
AR# 70289
日期 12/09/2020
状态 Active
Type 版本说明
IP
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