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AR# 70581

LogiCORE IP MIPI D-PHY Controller v4.0 (rev.1) (or MIPI CSI-2 Receiver Subsystem v3.0 (Rev. 1)) - Why do I see SoT/ECC/CRC errors on MIPI RX IP targeting UltraScale+ devices?

描述

Why do I see SoT/ECC/CRC errors on MIPI RX IP targeting UltraScale+ devices?

When using the MIPI D-PHY RX IP (or MIPI CSI-2 Receiver Subsystem) targeting UltraScale+ device, users can experience SoT/ECC/CRC errors on some of the UltraScale+ devices, even when the image-sensor seems to have the correct Global operation timing parameters set.

解决方案

This issue is reported with the MIPI D-PHY RX IP (or MIPI CSI-2 Receiver Subsystem) when the IP is generated using Vivado 2017.2, 2017.3 and 2017.4.

This issue occurs on some devices, when the image-sensor is set to non-continuous clock mode.

(No issue is observed when the image-sensor is set to Continuous clock mode).

The Fluctuating input signal of the MIPI D-PHY clock lane during the LP --> HS mode transition can trigger the capture of some invalid data in data lane FIFO which lead to SoT/ECC/CRC errors.

This issue will be fixed in Vivado 2018.1.

  • If you are using the Vivado 2017.4 version, you can download the LogiCORE IP MIPI D-PHY Controller v4.0 patch from (Xilinx Answer 70530).
  • If you are using Vivado 2017.2, 2017.3, or older versions, you will need to upgrade your design to the 2017.4 version before applying the patch. It is recommended that all users migrate to Vivado 2018.1.


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AR# 70581
日期 03/21/2018
状态 Active
Type 综合文章
器件
Tools
IP
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