AR# 70702

Zynq UltraScale+ MPSoC - PS/PL PCIe Drivers - Release Notes


This answer record contains known Issues and information related to the drivers for PS PCIe in Zynq UltraScale+ MPSoC.

This also includes information on the PL Root Port Solution (Driver and IP usage) in relation to Zynq UltraScale+ MPSoC.

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express


Known Issues

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 69066)Zynq UltraScale+ MPSoC Controller for PCI Express (Vivado 2017.1) - Root Port Error: hwirq 0x4 is too large for dummy 2017.1


(Xilinx Answer 70703)Zynq UltraScale+ MPSoC (Vivado 2017.4) - Issue fixes in driver for DMA/Bridge Subsystem for PCIe in AXI Bridge mode (PL PCIe) configured as Root Port 2017.32018.1
(Xilinx Answer 69587) Zynq UltraScale+ MPSoC: Linux hangs when accessing PL peripheral by Yocto (2017.1 - 2017.4) - ILA / HW Manager usage with core in PetaLinux requires bootarg2017.1NA
(Xilinx Answer 71106)Zynq UltraScale+ MPSoC - PL PCIe Root Port Bridge (Vivado 2018.1) - MSI Interrupt handling causes downstream devices to time out2018.1NA
(Xilinx Answer 72389)Zynq UltraScale+ MPSoC (Vivado 2019.1) - PL-PCIe Root Port - Driver Compilation Fails2019.1NA, Patch Provided
(Xilinx Answer 72638)Zynq UltraScale+ MPSoC (Vivado 2019.1) - PL-PCIe Root Port - Multi-device MSI assignment broken2019.1NA, Patch Provided

Other Information:

(Xilinx Answer 70854)Zynq UltraScale+ MPSoC - DMA/Bridge Subsystem for PCI Express - PL Bridge Root Port - IP Setup tips for use with PL PCIe Root Port driver
(Xilinx Answer 65443)DMA Subsystem for PCI Express - Release Notes and Known Issues for Vivado 2015.3 and newer tool versions

Related Answer Records on DMA/Bridge Subsystem for PCI Express:

(Xilinx Answer 70706)DMA/Bridge Subsystem for PCI Express (Bridge Mode/Root Port - Vivado 2017.4) - AXI transactions fail when no Endpoint is connected
(Xilinx Answer 71094)Zynq UltraScale+ MPSoC - DMA/Bridge Subsystem for PCIe (AXI Bridge mode/Root Port - Vivado 2018.1) - When 64-bit address is set in AXIBAR2PCIEBAR, endpoint PCIe BAR not enumerated in correct locations
(Xilinx Answer 71095)DMA / Bridge Subsystem for PCI Express (Bridge Mode - Vivado 2017.4) - AXIBAR and AXIBAR_HIGHADDR are set incorrectly in IPI design resulting in DECERR during 64-bit S_AXI access
(Xilinx Answer 71105)DMA Subsystem for PCI Express (Vivado 2018.1) - MSI Interrupt FIFO can overflow in Root Port configuration in Bridge Mode

Note: See (Xilinx Answer 65443) for other related information

Design Advisory:

(Xilinx Answer 70838)Design Advisory for AXI SmartConnect with PCI Express IP - Interoperability Issue - Data request upsize causes potential data corruption

Revision History:

06/03/2018 - Initial Release




Answer Number 问答标题 问题版本 已解决问题的版本
65443 DMA Subsystem for PCI Express - Release Notes and Known Issues for Vivado 2015.3 and newer tool versions N/A N/A
AR# 70702
日期 08/23/2019
状态 Active
Type 版本说明