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AR# 70720

Soft-Decision FEC (SDFEC) Integrated Block - Release Notes and Known Issues for Vivado 2018.1 and newer tool versions Article


This answer record contains the Release Notes and Known Issues for the Soft-Decision FEC (SDFEC) Integrated Block and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2018.1 and newer tool versions.

Soft-Decision FEC Integrated Block Page

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General Information

Supported devices can be found in the following three locations:

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

SDFEC IP Version Vivado Version Vivado IP Change Log IP Patch
v1.1 Rev 4 2019.2 (Xilinx Answer 72923)  
v1.1 Rev 3 2019.1 (Xilinx Answer 72242)  
v1.1 Rev 2 2018.3 (Xilinx Answer 71806) (Xilinx Answer 71873)
v1.1 Rev 1 2018.2 (Xilinx Answer 71212) (Xilinx Answer 71347)
v1.1 2018.1 (Xilinx Answer 70699) (Xilinx Answer 71341)


Known and Resolved Issues


Answer Record Title Version 
(Xilinx Answer 71823) Simulation only example design generates incorrect stimulus on Windows OS v1.1 Rev 1 v1.1 Rev 3
(Xilinx Answer 71876) Why do I get error "MSG: Uncaught exception in model create" when building C-model executable? v1.1 Rev 1 v1.1 Rev 3
(Xilinx Answer 71415) No DRC check for -2LVI device family even when LDPC placement and frequency violates the requirement v1.1 Rev 1 v1.1 Rev 2
(Xilinx Answer 71362) Incorrect behavior when configured with an Initialized parameter interface (S_AXI) 
v1.1 v1.1 Rev 2
(Xilinx Answer 71060) (PG256) - Runtime Loading GUI tab information is out of date for Vivado 2018.2
v1.1Rev1 v1.1 Rev 2


Revision History

12/21/2018 Added (Xilinx Answer 71876) and (Xilinx Answer 71823)
08/10/2018 Added (Xilinx Answer 71415)
07/27/2018 Added (Xilinx Answer 71362), and (Xilinx Answer 71060)
03/22/2018 Initial Release



AR# 70720
日期 11/22/2019
状态 Active
Type 版本说明