AR# 70875

AXI 1G/2.5G Ethernet - Vivado 2018.1 and earlier - UltraScale/UltraScale+ SGMII or 1000BASE-X over LVDS - Link failure sometimes after reset


When generating the AXI Ethernet core for Asynchronous SGMII or 1000BASE-X over LVDS with the shared logic in the example design, there is a issue with the reset logic that can sometimes result in link failure.


In the example design file core_name_support.v the logical AND should be changed to a logical OR in the below code.

Original version:

assign local_reset = Tx_Logic_Rst_int && Rx_Logic_Rst_int;

Updated Version:

assign local_reset = Tx_Logic_Rst_int || Rx_Logic_Rst_int;

The AXI Ethernet core and example design without shared logic is not affected.

The 1G/2.5G Ethernet PCS/PMA core and example design are also not affected by this issue.

This issue is scheduled to be fixed in Vivado 2018.2.

AR# 70875
日期 09/24/2018
状态 Active
Type 综合文章