In Vivado 2018.1 and earlier versions, when generating the 25G, 50G, 100G or Flex-O RS-FEC cores on a Windows machine, the RX and TX alignment markers in the RS-FEC example design are incorrect.
The upper 32-bits of each alignment marker is incorrectly tied to 0 in the core_name_exdes.v file.
For example, for 100G:
To work around this issue, the example design can be generated on a Linux machine or the RX and TX alignment marker values can be updated manually in the core_name_exdes.v file.
This issue only applies to the stand-alone RS-FEC core example design and does not affect the RS-FEC core itself or any cores such as the 25G/50G/100G Ethernet Subsystems that use the RS-FEC as a subcore.
This issue is scheduled to be fixed in Vivado 2018.2.