When the using the 10G/25G Ethernet Subsystem configured for the following, there is an error in the signal connections for the RS-FEC enable:
Other configuration, without AXI4-Lite or with only 25G line rate are not affected.
Linked below are patches for the 2017.3 and 2018.1 releases. This issue is scheduled to be fixed in Vivado 2018.2.
The 2018.1 patch also includes fixes for the following issues (The 2017.3/2017.4 versions do not have these issues):
|(Xilinx Answer 71098)||10G/25G Ethernet Subsystem - 2018.1 - Synthesis error seen when using PCS Only Configuration in IP Integrator block diagram|
|(Xilinx Answer 71099)||10G/25G Ethernet Subsystem - 2018.1 - PCS only configuration contains hardware timeout|