UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7097

FPGA Express 3.x: Virtex/E flip flops are not merged into the IOB

Description

Keywords: Foundation, Express, Synopsys, Virtex, flop, I/O, merge, register

Urgency: Standard

General Description:
By default, for all families except Virtex/E, FPGA Express will attempt to merge registers into
IOBs whenever possible. This behavior can be controlled in the Express Constraints Editor
under the Ports tab by modifying the value under the column heading "Use I/O Reg".

Setting the default value to TRUE does not work for Virtex/E designs.

解决方案

1

This functionality can be achieved on a global level by setting the -pr option in MAP. Set
this to "I" for inputs, "O" for outputs, or "B" for both inputs and outputs. This option can be
set in the Implementation options GUI.

2

Setting the default "Use I/O Reg" value to TRUE does not work, but setting this value on
individual ports does. Set Use I/O Reg to TRUE for each port that should have a flip flop
merged into it. This will not, however, work for tri-state enable flip flops.

This problem is fixed starting with version 3.4.

AR# 7097
创建日期 07/23/1999
Last Updated 08/27/2001
状态 Archive
Type 综合文章