AR# 71045

2017.3-2018.1 Zynq UltraScale+ MPSoC: DMA/AXI Bridge for PCI Express Subsystem - Bridge Root Port mode - pcie-xdma-pl driver - AXIBAR0 configured in upper address space will result in incomplete S_AXIB transactions


In Zynq UltraScale+ devices, use of a low/high address in the upper 64-bit address space, or an AXIBAR2PCIEBAR_0 translation address in the upper-64 bit space for AXIBAR0 will lead to "Unexpected Request" from the attached endpoint device due to an address translation error.

At the AXI User Interface, the S_AXIB_AR transactions will return as a SLVERR - UR.

s_axib_rresp = 'h3

S_AXIB_AW transactions will not complete at the endpoint device.


This is a known issue for Zynq UltraScale+ MPSoC with the DMA/AXI Bridge for the PCI Express Subsystem.

The AXIBAR0 of the Root Port must be configured with a Low and High address in the lower 32-bit address space, and the AXIBAR2PCIEBAR_0 translation address must also be in the lower 32 bits of address space.

AXIBAR_1 and up can be configured with a 64-bit low and high address.

Note: The "Version Found" column lists the version the problem was first discovered. 

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

AR# 71045
日期 04/23/2018
状态 Active
Type 已知问题
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