AR# 71147

DMA / Bridge Subsystem for PCI Express (Vivado 2018.1) - Tactical patch for issue fixes


Version Found: v4.1

Version Resolved and other Known Issues: (Xilinx Answer 65443)

The tactical patch provided with this answer record contains the following fixes for issues in DMA / Bridge Subsystem for PCI Express in Vivado 2018.1.  

This patch contains all previously released fixes for the 2018.1 version, detailed in (Xilinx Answer 65443).


  • Bug Fix: Fixed TLP ordering issue on Slave AXI Lite and Slave AXI Interfaces
  • Bug Fix: Fixed Master MemWr and received interrupt ordering issue for AXI Bridge RC configuration
  • Bug Fix: Fix for CQ NP credits after Partial Reconfiguration
  • Bug Fix: Fix for [Synth 8-488] error when synthesizing XDMA IP with IBERT enabled
  • Bug Fix: Fixed for 7 Series Gen2 DMA hang issue due to TLP drop and incorrect TLP for straddled packets
  • Bug Fix: Fix for Artix-7 GT COMMON placement error, when selecting the GT COMMON to Example Design
  • Bug Fix: Enabled txprgdivresetdone_out port from GT Wizard to fix issue with 125/250 Mhz reference clock with Gen1 

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express


The issues listed in this answer record will be fixed in a future release of the core.

For instructions on installing the patch, please check the instructions in the 'patch_readme' directory in the attached patch file.

Note: the "Version Found" column lists the version the problem was first discovered. 

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

06/06/2018 - Initial Release


文件名 文件大小 File Type 8 MB ZIP



Answer Number 问答标题 问题版本 已解决问题的版本
65443 DMA Subsystem for PCI Express - Release Notes and Known Issues for Vivado 2015.3 and newer tool versions N/A N/A


AR# 71147
日期 06/06/2018
状态 Active
Type 已知问题