AR# 71165

Virtex UltraScale+ HBM Controller performance is low when only 1 AXI port is used in a 2 stack design


Version Found: HBM v1.0

Version Resolved: See (Xilinx Answer 69267)

The switch in each stack is clocked by one of the AXI clocks for that stack. 

This is auto-selected by the IP Wizard. If there are 8 AXI ports in use, the Wizard will select a clock that is most centrally located to the enabled AXI ports (this can be overridden by the user by manually selecting a different AXI clock).

In the event that a stack is enabled but no AXI ports are enabled, the software chooses the HBM reference clock which might not be at a frequency ideal for the switch.

Ideally, the switch should run as fast as the fastest AXI clock. 

So in a situation where stack 0 has one AXI port running at 450 MHz, and stack 1 has no AXI ports, the software does not see a AXI clock to use for the switch in stack 1.

As a result it takes the HBM reference clock, which might be at a frequency of less than 450, and therefore creates a performance bottleneck.


The work-around is to enable a single AXI port on the stack with no AXI ports (stack 1 in the example above), ensure that it is running at the same frequency as the AXI port that is in use, and the tools then will automatically select it for use to clock the switch.

This issue will be fixed in the 2018.3 release.

Change Log:

05/30/18 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
69267 Virtex UltraScale+ HBM 控制器 - 发布说明与已知问题 N/A N/A
AR# 71165
日期 06/18/2018
状态 Active
Type 综合文章