How should I connect up the VCU Encoder and Decoder Memory Map ports to the Zynq UltraScale+ MPSoC AFI interfaces?
This is dependent on the configuration of the VCU.
Users should open the VCU GUI and obtain a more precise number for the bandwidth requirements, then configure based on their particular VCU configuration.
Some general Guidelines:
The following are example calculations.
The specific bandwidth varies depending on the max resolution and use of the Encoder buffer or Multi-stream configurations.
Xilinx recommends that you group like traffic patterns for better efficiency.
For applications using the max resolution, it is recommended that you do a 1:1 mapping of encoder and decoder ports to each AFI, with the combined capture and display traffic using one AFI (traffic class is the same and has a max bandwidth for 4:2:2, 10-bit of ~2.6 GB/s).
This is done in order to avoid saturating the AFI interface.
For example if no encoder buffer is used you would use the following:
However as noted above, when the Encoder buffer is used, the aggregate bandwidth is less than the AFI max, and a user could combine the Encoder interfaces and share a single AFI interface, as shown below: