Version Found: v2.8 (Rev9)
Version Resolved and other Known Issues: See (Xilinx Answer 54646)
In a block design containing AXI Bridge for PCI Express IP, the offset addresses set in the address editor is not correctly reflected in the IP.
If the following offsets are set in the address editor for BAR0, BAR1 and BAR2 respectively,
the generated XCI for AXI Bridge for PCI Express IP will contain the following:
MODELPARAM_VALUE.C_AXIBAR_0 will be 0x50000000
MODELPARAM_VALUE.C_AXIBAR_1 will be 0x30000000
MODELPARAM_VALUE.C_AXIBAR_2 will be 0x40000000
C_AXIBAR_0 is correct but C_AXIBAR_1 and C_AXIBAR_2 values are not correct. They should be 0x60000000 and 0x70000000 respectively.
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
This is a known issue which is planned to be fixed in a future release of the core.
To fix the issue in Vivado 2018.2, please install the tactical patch attached to this answer record.
For instructions on installing the patch, see the readme file in the patch.
After the patch is installed, the version of the AXI Memory Mapped to PCI Express core should indicate: v2.8 (Rev. 71252).
07/02/2018 - Initial release