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MIPI D-PHY - UltraScale+ devices - Two independent IP instances in the same bank need to be reset at the same time
In a design with two independent D-PHY instances placed in the same bank, resetting the cores at different times can cause issues.
Why does this occur?
When multiple D-PHY IPs are placed in the same bank, they need to be reset at the same time even if they are independent.
This is a silicon limitation mentioned in (UG571):
- Kintex UltraScale+
- Virtex UltraScale+
- Zynq UltraScale+ MPSoC
- Zynq UltraScale+ RFSoC