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AR# 71374

MIPI D-PHY - UltraScale+ devices - Two independent IP instances in the same bank need to be reset at the same time

描述

In a design with two independent D-PHY instances placed in the same bank, resetting the cores at different times can cause issues.

Why does this occur?

解决方案

When multiple D-PHY IPs are placed in the same bank, they need to be reset at the same time even if they are independent.

This is a silicon limitation mentioned in (UG571):





链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54550 LogiCORE IP MIPI D-PHY - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A
AR# 71374
日期 07/27/2018
状态 Active
Type 综合文章
器件
  • Kintex UltraScale+
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Zynq UltraScale+ RFSoC
IP
  • MIPI D-PHY
的页面