AR# 71399

UltraScale+ PCI Express 4c Integrated Block - Release Notes and Known Issue


  • This answer record contains the Release Notes and Known Issues for the UltraScale+ PCI Express 4c Integrated Block Core and includes the following:
  • General Information
  • Known and Resolved Issues
  • Revision History

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Xilinx Forums:

Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.


Supported devices can be found in the following locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v1.0 (Rev8) 2020.1
v1.0 (Rev6) 2019.2
v1.0 (Rev5) 2019.1
v1.0 (Rev4) 2018.3
v1.0 (Rev3) 2018.2
v1.0 (Rev2) 2018.1
v1.0 (Rev1) 2017.4
v1.0 2017.3

Tactical Patch

The following table provides a list of tactical patches for the UltraScale+ PCI Express 4c Integrated Block core applicable on corresponding Vivado tool versions.

Answer Record Core Version (After installing the Patch) Tool Version
(Xilinx Answer 75334) v1.0 (Rev 75334) 2020.1
(Xilinx Answer 73417) v1.0 (Rev 73417) 2019.2
(Xilinx Answer 71498) v1.0 (Rev 71498)

Known and Resolved Issues

The following table provides known issues for the UltraScale+ PCI Express Integrated Block core, starting with v1.0, initially released in Vivado 2017.3.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version Found Version Resolved
(Xilinx Answer 75334) Tactical Patch for Issue Fixes:
  • Bug Fix: Fixed VU19P device support issue
 Vivado 2020.1 Not Resolved Yet
Tactical Patch Provided
(Xilinx Answer 73417) Tactical Patch for Issue Fixes:
  • CPLL fails to lock in when reference clock is set to 250MHz at Gen1 rate with PCIe IP
Vivado 2019.2 Vivado 2020.1
(Xilinx Answer 71498) MCP (Multi Cycle Path) Constraints on RQSEQNUM* signal missing for ES1 parts Vivado 2018.2 Vivado 2018.3
(Xilinx Answer 71375) Link does not train in Gen1 design with Refclk at 125MHz and 250MHz speeds Vivado 2018.1 Vivado 2018.2


Other Information:

(Xilinx Answer 75490) Vivado 2020.1.1 - GTYCHK-1 and GTYCHK-2 DRC Violations


Revision History:

  • 08/01/2018 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
73417 PCI Express Integrated Block (Vivado 2019.2) - CPLL fails to lock in when reference clock is set to 250MHz at Gen1 rate N/A N/A
AR# 71399
日期 08/31/2020
状态 Active
Type 版本说明