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  3. AR# 7140: 3.x FPGA Express - How do I infer ROM for Virtex, Virtex-E and Virtex-II?

AR# 7140

3.x FPGA Express - How do I infer ROM for Virtex, Virtex-E and Virtex-II?

描述

Keywords: Synopsys, FPGA Express, 3.3, 3.5, infer, ROM, primitive, Virtex, Virtex-E, Virtex-II, select-RAM, block, RAM

Urgency: Standard

General Description:
How do I infer ROM for Virtex, Virtex-E and Virtex-II?

解决方案

1

FPGA Express versions 3.3 and above have the ability to infer ROM primitives for Virtex designs if the syntax described below is used. Three points must be noted:

1. Be sure to define at least 75% of the states. (50% of the states may be defined if the "infer_mux" attribute is used.)

2. These components will be written into the EDIF netlist as LUT4s, not ROM16X1s. Either one will be implemented identically.

3. This feature is only applicable to Virtex-based architectures.

Currently, FPGA Express can not infer RAM.

Beginning with FPGA Express 3.5 for Virtex, Virtex-E, and Virtex-II, block RAM for ROMs (rather than LUTs) will be inferred in the following cases:

For Virtex and Virtex-E: Block RAM will be inferred when the address line is at least 10 bits, and the data line is 3 bits or greater. Also, block RAM will be inferred when the address line is 11 or 12 bits; no minimum data width is required.

For Virtex-II: Block RAM will be inferred for ROM if the address line is between 10 to 14 bits; no minimum data width is required.

For more information on the "infer_mux" attribute, please refer to (Xilinx Answer 11331).


- The following VHDL code will be implemented in eight LUTs (two for each output bit):

process (ADDRESS)
begin
case ADDRESS is
when "00000" => output <= "1110" ;
when "00001" => output <= "0100" ;
when "00010" => output <= "1101" ;
when "00011" => output <= "0001" ;
when "00100" => output <= "0010" ;
when "00101" => output <= "1111" ;
when "00110" => output <= "1011" ;
when "00111" => output <= "1000" ;
when "01000" => output <= "0011" ;
when "01001" => output <= "1010" ;
when "01010" => output <= "0110" ;
when "01011" => output <= "1100" ;
when "01100" => output <= "0101" ;
when "01101" => output <= "1001" ;
when "01110" => output <= "0000" ;
when "01111" => output <= "0111" ;
when "10000" => output <= "0000" ;
when "10001" => output <= "1111" ;
when "10010" => output <= "0111" ;
when "10011" => output <= "0100" ;
when "10100" => output <= "1110" ;
when "10101" => output <= "0010" ;
when "10110" => output <= "1101" ;
when "10111" => output <= "0001" ;
when "11000" => output <= "1010" ;
when "11001" => output <= "0110" ;
when "11010" => output <= "1100" ;
when "11011" => output <= "1011" ;
when "11100" => output <= "1001" ;
when "11101" => output <= "0101" ;
when "11110" => output <= "0011" ;
when "11111" => output <= "1101" ;
when others => output <= "1101";
end case;
end process;

- The following VHDL code will be implemented in eight LUTs (two for each output bit) using the "infer_mux" attribute:

process (ADDRESS)
begin
case ADDRESS is -- synopsys infer_mux
when "00000" => output <= "1110" ;
when "00001" => output <= "0100" ;
when "00010" => output <= "1101" ;
when "00011" => output <= "0001" ;
when "00100" => output <= "0010" ;
when "00101" => output <= "1111" ;
when "00110" => output <= "1011" ;
when "00111" => output <= "1000" ;
when "01000" => output <= "0011" ;
when "01001" => output <= "1010" ;
when "01010" => output <= "0110" ;
when "01011" => output <= "1100" ;
when "01100" => output <= "0101" ;
when "01101" => output <= "1001" ;
when "01110" => output <= "0000" ;
when "01111" => output <= "0111" ;
when "10000" => output <= "0000" ;
when others => output <= "1101";
end case;
end process;

NOTE: A bug in FPGA Express prevents a ROM that is using Block RAM from being properly inferred.

This problem is fixed in the latest 4.2i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.2i Service Pack 2.

Please download and install the FPGA Express version that is available with 4.1i Service Pack 2.

2

- The following Verilog code will be implemented in eight LUTs (two for each output bit):

always@(address)
begin
case (address)
5'b00000: romout = 4'b1110;
5'b00001: romout = 4'b0100;
5'b00010: romout = 4'b1101;
5'b00011: romout = 4'b0001;
5'b00100: romout = 4'b0010;
5'b00101: romout = 4'b1111;
5'b00110: romout = 4'b1011;
5'b00111: romout = 4'b1000;
5'b01000: romout = 4'b0011;
5'b01001: romout = 4'b1010;
5'b01010: romout = 4'b0110;
5'b01011: romout = 4'b1100;
5'b01100: romout = 4'b0101;
5'b01101: romout = 4'b1001;
5'b01110: romout = 4'b0000;
5'b01111: romout = 4'b0111;
5'b10000: romout = 4'b0000;
5'b10001: romout = 4'b1111;
5'b10010: romout = 4'b0111;
5'b10011: romout = 4'b0100;
5'b10100: romout = 4'b1110;
5'b10101: romout = 4'b0010;
5'b10110: romout = 4'b1101;
5'b10111: romout = 4'b0001;
5'b11000: romout = 4'b1010;
5'b11001: romout = 4'b0110;
5'b11010: romout = 4'b1100;
5'b11011: romout = 4'b1011;
5'b11100: romout = 4'b1001;
5'b11101: romout = 4'b0101;
5'b11110: romout = 4'b0011;
5'b11111: romout = 4'b1101;
default: romout = 4'b1101;
endcase
end

- The following Verilog code will be implemented in eight LUTs (two for each output bit) using the "infer_mux" attribute:

always@(address)
begin
case (address) // synopsys infer_mux
5'b00000: romout = 4'b1110;
5'b00001: romout = 4'b0100;
5'b00010: romout = 4'b1101;
5'b00011: romout = 4'b0001;
5'b00100: romout = 4'b0010;
5'b00101: romout = 4'b1111;
5'b00110: romout = 4'b1011;
5'b00111: romout = 4'b1000;
5'b01000: romout = 4'b0011;
5'b01001: romout = 4'b1010;
5'b01010: romout = 4'b0110;
5'b01011: romout = 4'b1100;
5'b01100: romout = 4'b0101;
5'b01101: romout = 4'b1001;
5'b01110: romout = 4'b0000;
5'b01111: romout = 4'b0111;
5'b10000: romout = 4'b0000;
default: romout = 4'b1101;
endcase
end

NOTE: A bug in FPGA Express prevents a ROM that is using Block RAM from being properly inferred.

This problem is fixed in the latest 4.2i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.2i Service Pack 2.

Please download and install the FPGA Express version that is available with 4.1i Service Pack 2.
AR# 7140
日期 08/11/2003
状态 Archive
Type 综合文章
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