AR# 71400

UltraScale/UltraScale+ QDRII+ IP - Byte 3 of a 36-bit QDRII+ Interface Not Showing Calibration Margins in the Hardware Manager

描述

Version Found: V1.4 

Version Resolved: See (Xilinx Answer 69038)

When using QDRII+ components that have a single 36-bit interface, the last byte of the interface will not report any calibration margins in the Vivado Hardware Manager.  

This only happens for 36-bit native parts, and not for 18-bit or when using two 18-bit interfaces to make a single 36-bit interface.  

The Hardware Manager will still report a CAL PASS status but the "Table" view of "Calibration and Margins" will show 0 ps Left and Right margin as well as a 0 ps Center point for Byte 3.  

When changed to the "Chart" view, Byte 3 will show a solid red bar across the timescale.


This behavior is caused by a limitation in the XSDB tools in the Hardware Manager.  

The tools to generate the calibration margin information in the Hardware Manager GUI were designed around the assumption that only a single 'byte' of a memory interface will be able to fit within a single Select I/O byte in the FPGA.  

QDRII+ 36-Bit components are unique in that 4 bytes of the interface can fit within 3 bytes of Select I/O.  

Due to this behavior the tools are unable to understand that the last byte of the QDRII+ interface still needs the calibration margins to be calculated from the XSDB data and presented in the Hardware Manager GUI.  

Unfortunately this behavior will not be corrected in future versions of the tools.

解决方案

Even though no margin is reported for Byte 3, as long as the MIG Status says CAL PASS then the interface has passed calibration with sufficient margin.

If there is a calibration error of any sort then the MIG Status will report CAL FAIL. If there is insufficient margin on Byte 3 (less than 30% of the UI) then the Message status will report that a narrow window was detected. 


To work around this behavior and get a visual representation of the Byte 3 calibration, simply remap the byte in your XDC pin constraints to a different byte in the design. 

For example you can swap Byte 3 with Byte 0. When you view the results in the Hardware Manager, Byte 0 now represents the calibration margins from the physical Byte 3 on the board. 

Because Byte 0 is now mapped to Byte 3 you will not be able to see these margins, but you will know the margins that were reported from the previous builds. 


Additionally you can dump the XSDB data after calibration is complete and compare the calibration results of Byte 3 to the other bytes in the design.

If the results are consistent with the other bytes then you know that the byte has sufficient margin.

Here is the command to dump the XSDB data:

report_property file xsdb_dump.txt [lindex [get_hw_migs] 0]

Revision History:

05/09/2019 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69038 UltraScale/UltraScale+ QDRII+ - Release Notes and Known Issues N/A N/A
AR# 71400
日期 05/09/2019
状态 Active
Type 已知问题
器件 More Less
Tools
IP