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AR# 71795

Virtex UltraScale+ HBM Controller - Simulation Errors Seen when HBM Memory is Operating at Frequencies Other than 900MHz

描述

Version Found: HBM v1.0

Version Resolved: See (Xilinx Answer 69267) 

When performing HBM simulations in Questa, IES, or VCS with the HBM Memory Stack configured to operate at any frequency other than 900MHz, simulation errors will occur. 

Simulation will generate timing violation messages, and depending on the configuration this could result in data mismatches or read commands that do not generate a read response + data. 

Production Virtex UltraScale+ HBM -1 speed grade devices have an 800MHz FMAX for the memory and will encounter simulation errors.  

These simulation errors are related to the timing requirements generated by the IP core, and the HBM memory model which does not adjust to memory frequencies lower than 900MHz. 

These errors only occur in simulation. Hardware functionally is not affected.

解决方案

The work-around for this behavior is to use the default timing values for the simulation model.

To do this, you will need to modify the xpm_internal_config_file_sim_0.sim file for Stack 0 and the xpm_internal_config_file_sim_0.sim file for Stack 1.

For a default project these files can be found in the /proj_name.srcs/sources_1/ip/hbm_0_hdl/rtl directory. 

Each memory channel has 36 consecutive lines of text that need to be deleted. Use the table below to find the starting offset for each channel:

Memory Channel NumberStarting Offset Value
MC0 / MC80010_
MC1 / MC9
0018_
MC2/ MC10
0012_
MC3 / MC11
001A_
MC4 / MC12
0014_
MC5 / MC13
001C_
MC6 / MC14
0016_
MC7 / MC15
001E_


Open the xpm_internal_config_file_sim_x.mem file and search for 0010_4054 for MC0. Select this line and the consecutive 35 lines from this point for a total of 36 lines.

Delete these lines and save the file. After removing these 36 lines there will still be additional lines in the file that start with 0010_ which need to remain untouched:



Perform this same flow for the remaining memory channels that are enabled in the design.

The HBM memory model will be updated in a future release of Vivado to address this behavior.

Revision History:

12/17/2018 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69267 Virtex UltraScale+ HBM Controller - Release Notes and Known Issues N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
71097 Virtex UltraScale+ HBM - Example Design Simulation Issues with VCS, Questa Sim, or IES N/A N/A
AR# 71795
日期 01/08/2019
状态 Active
Type 已知问题
器件
Tools
IP
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