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AR# 71894

Virtex UltraScale+ HBM Controller - DRAM_y_STAT_TEMP Port Behavior Change in 2018.3 version

描述

Version Found: HBM v1.0 (Rev. 2)

Version Resolved: See (Xilinx Answer 69267)

In the 2018.3 version of the HBM IP, the DRAM_y_STAT_TEMP port behavior has changed.

In the 2018.2 version, STAT_TEMP output reported the required refresh interval for the HBM memory stack, which users could extrapolate to approximate temperature ranges.

In the 2018.3 version, the STAT_TEMP output is now 7 bits wide and is the HBM memory stack temperature in Celsius.

In the case when two HBM stacks are enabled and the temperatures are over 5C, it will report the higher of the two stacks.

When the temperatures are below 5C it will report the lower of the two stacks.

The temperature update rate is controllable in the HBM Configuration Selection tab of the IP GUI under the APB Clocking section in the Temperature Polling Interval field.


 

解决方案

In the next release of (PG276) the DRAM_y_STAT_TEMP description in Table 5 will be updated to reflect the new behavior in the 2018.3 release.

Revision History:

01/07/2019 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69267 Virtex UltraScale+ HBM Controller - Release Notes and Known Issues N/A N/A
AR# 71894
日期 01/08/2019
状态 Active
Type 已知问题
器件
Tools
IP
的页面