AR# 71984

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AXI VDMA v6.3 - Design on a 7 Series device fails to meet timing with a VDMA in asynchronous mode

描述

In Vivado 2017.3 to 2018.3, a design using the AXI Video Direct memory Access (VDMA) IP core in asynchronous mode targeting a 7 Series device might fail timing with a failing path located inside the VDMA.

What is the cause of this issue and how can it be resolved?

解决方案

The automatically generated constraints file for the AXI VDMA core is missing constraints, which causes the timing to fail.

As a work-around, you can add the following constraints to your design:

set_false_path -from [get_cells -hierarchical  -filter "NAME =~*<ip_instance_name>*MM2S*LB_BUILT_IN*/*rstbt*/*rst_reg[*]"]
set_false_path -from [get_cells -hierarchical  -filter "NAME =~*<ip_instance_name>*MM2S*LB_BUILT_IN*/*rstbt*/*rst_reg_reg"]
set_false_path -to   [get_pins  -hierarchical  -filter "NAME =~*<ip_instance_name>*MM2S*LB_BUILT_IN*/*rstbt*/*PRE"]
set_false_path -to   [get_pins  -hierarchical  -filter "NAME =~*<ip_instance_name>*S2MM*LB_BUILT_IN*/*rstbt*/*PRE"]
set_false_path -from [get_cells -hierarchical  -filter "NAME =~*<ip_instance_name>*S2MM*LB_BUILT_IN*/*rstbt*/*rst_reg_reg && IS_SEQUENTIAL"]
set_false_path -from [get_cells -hierarchical  -filter "NAME =~*<ip_instance_name>*S2MM*LB_BUILT_IN*/*rstbt*/*rst_reg[*]"]

Notes:

  1. <ip_instance_name> should be replaced with the instance name of the AXI VDMA IP core
  2. These constraints should be added only for an AXI VDMA IP configured in asynchronous mode
  3. These constraints should be added only for a design targeting a 7 Series device


This issue is resolved in Vivado 2019.1.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54448 LogiCORE IP AXI Video Direct Memory Access - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 71984
日期 12/12/2019
状态 Active
Type 已知问题
IP
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