AR# 72059

Zynq UltraScale+ MPSoC, Vivado 2018.2 - PS DDR fails when setting auto self-refresh


In Vivado 2018.2 I am trying to change the "Low-Power Auto Self-Refresh" option under the "Refresh mode Settings" for DDR configuration.

When I change it from "manual normal" (default) to "auto self-refresh" in order to test the DDR4 with the Zynq UltraScale+ MPSoC DRAM test template application, it fails with memory errors.


This is a known issue with the 2018.2 version of the IP.


In the psu_init.tcl/.c file, search for the DDR_PHY_MR2_OFFSET register and in the auto-self-refresh case set it based on your DDR speed bin configuration:

  • If you are using a Speed Bin of 2400MT/s replace it with:  0x000000E8U.
  • If you are using a Speed Bin of 2133MT/s replace it with:  0x000000E0U.

The issue has been fixed in Vivado 2018.3 and no manual changes are needed from this version.

AR# 72059
日期 03/12/2020
状态 Active
Type 已知问题
Boards & Kits