AR# 72290


2019.1 Zynq UltraScale+ MPSoC: USB 3.0 getting missed Interval for Isochronous transfers when operating in Super-Speed Mode


When Isochronous transfers are operated in super-speed mode with bInterval = 1, the controller generates Missed Interval events and issues BUS EXPIRY.



Avoid making the controller go into U1/U2 LPM states. 

This can be done by sending a 0 value for U1DevExitLat and U2DevExitLat in the BOS descriptor. 

On seeing U1DevExitLat and U2DevExitLat as 0, the host does not issue U1/U2 transactions on the link, thus avoiding the BUS EXPIRY and Missed Interval events for Isochronous transfers.


The Controller issues BUS EXPIRY when the driver tries to issue Isochronous transfers, causing applications such as Audio/Video to fail to send data.

AR# 72290
日期 09/03/2019
状态 Active
Type 已知问题
Boards & Kits
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