UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7240

FPGA Express - Is it possible to infer signed arithmetic modules in VHDL or Verilog?

Description

Keywords: signed, Verilog, Express, modules

Urgency: Standard

General Description:
Is it possible to infer signed arithmetic modules in VHDL or Verilog?

解决方案

1

VHDL

Signed modules can be inferred, but it is currently not possible to infer both signed and unsigned operators in the same entity-architecture pair.

Please see the FPGA Express online help topic "Arithmetic and Relational Module Inference Examples" for examples and more information.

2

Verilog

Currently, it is not possible to infer signed modules in Verilog.

For more information, please refer to the FPGA Express online help topic "Arithmetic and Relational Module Inference Examples".
AR# 7240
创建日期 08/11/1999
Last Updated 08/11/2003
状态 Archive
Type 综合文章