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AR# 72449

SMPTE UHD-SDI RX/TX Subsystem - UltraScale+ GTH/GTY - Why do I see link errors on the TX when using QPLL0 and QPLL1 to switch line rates on the RX between 11.88 Gbps and 11.88/1.001 Gbps?

描述

Why do I see link errors on the TX when using QPLL0 and QPLL1 to switch line rates on the RX between 11.88 Gbps and 11.88/1.001 Gbps?

I am using the SMPTE UHD-SDI IP and SMPTE UHD-SDI Receiver and Transmitter Subsystems with QPLL0/1 as shown in the diagram below.

Switching the SMPTE UHD-SDI Receiver from 11.88Gbps to 11.88/1.001Gbps can inject errors into the SMPTE UHD=SDI Transmitter channel resulting in CRC errors at the 12G-SDI Sink.

Example:

  • SMPTE UHD-SDI Receiver Line rate is 12G-SDI.
  • SMPTE UHD-SDI Transmitter is at 12G-SDI 3840x2160 @60 Hz
  • SMPTE UHD-SDI Receiver switches from 3840x2160 @59.94 <----> 3840x2160@ 60Hz
  • Errors injected into the SMPTE UHD-SDI Transmitter
  • The far-end 12G-SDI Sink shows CRC errors due to the errors injected in the SMPTE UHD-SDI Transmitter

解决方案

This is due to a limitation of the UltraScale+ GTH/GTY that is addressed in (Xilinx Answer 72254).

This issue only applies to the SMPTE UHD-SDI Receiver and Transmitter in the below use case:

  • This only affects the 12G-SDI rates and does not affect SD/HD/3G/6G-SDI rates.
  • This issue only occurs when the SMPTE UHD-SDI Receiver and Transmitter are within the same RX/TX transceiver pair, but are operating independently and the SMPTE UHD-SDI Receiver switches between the integer and fractional rates.

 

For users who need both 12G-SDI Receive and Transmit and need them to operate independently, here are the recommended solutions:

  1. Users with -1 speed grade parts MUST use separate GTs for UHD-SDI Receiver and SMPTE UHD-SDI Transmitter
  2. Users with -2 or faster speed grade parts running at >=0.85V can use the CPLL for the UHD-SDI Transmitter and the QPLL0/1 for the UHD-SDI Receiver when configured as shown in the diagram below

 


 

For additional information see the following documentation:

  • (PG289) SMPTE UHD-SDI Transmitter Subsystem v2.0
  • (PG290) SMPTE UHD-SDI Receiver Subsystem v2.0

Example Designs:

The SMPTE UHD-SDI Receiver Subsystem - Audio-Video Loopback for the KCU116 board example design has been updated in the 2019.2 release and later versions to implement the above clocking recommendations.

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Answer Number 问答标题 问题版本 已解决问题的版本
72254 UltraScale+ GTH/GTY: Independent usage of TX / RX can be affected by TX / RX QPLL clock source switching N/A N/A
AR# 72449
日期 11/18/2019
状态 Active
Type 已知问题
器件
Tools
IP
Boards & Kits
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