AR# 72484

Vivado 2018.1/2018.2/2018.3: XPM_FIFO RTL Tactical Patch - sm_safe_state = "default_state" and Additional safe - exit mechanism from reset sequence in locked up condition.

描述

In Vivado 2018.1, 2018.2 and 2018.3, the FIFO can lock up in some scenarios.

A valid reset assertion does not bring the FIFO to a steady default state, and FPGA reconfiguration or a power cycle is required to come out of the locked state.

The XPM FIFO is a sub-core to IPs such as the AXI Chip2Chip and AXI4-Stream Clock Converter.

This issue can occurr in systems with these IPs. Applying the patches in the solution will resolve these issues.

解决方案

The reset sequence has been modified for XPM_FIFO in Vivado 2019.1 to address this issue.

For Vivado 2018.1, 2018.2 or 2018.3 you can use the patches attached to this Answer Record.

附件

AR# 72484
日期 08/11/2020
状态 Active
Type 综合文章
器件 More Less
Tools
IP