The most recently published version of the JEDEC LPDDR4 specification, JESD209-4B, introduced a requirement to drive DQS_c high for a period of time before and after every write burst (4.13 Write and Masked Write operation DQS controls (WDQS Control)) which details the following:
"Some legacy products may not provide WDQS control described below. However, in order to prevent the write preamble related failure, it is strongly recommended to support either of two WDQS controls to LPDDR4-SDRAMs.
In the case of legacy SoC which may not provide WDQS control modes, it is required to consult DRAM vendors to guarantee the write / masked write operation appropriately."
Increasingly, DRAM vendors are requiring this feature, such that all LPDDR4 designs should enable this behavior.
|Impact||The Zynq UltraScale+ PS LPDDR4 memory controller defaults to not providing the WDQS control suggested by the JEDEC specification.
Xilinx recommends updating all PS LPDDR4 designs.
At the time of publication of this Design Advisory, no functional failures have been observed, but customers should consult DRAM vendors to guarantee write/masked write operation if they choose not to upgrade their designs.
|Work-around||On the Processing System block in Vivado IP Integrator, set PSU_DDRC_VENDOR_PART=HYNIX.
This can be accomplished with a Vivado Tcl command similar to the following:
set_property CONFIG.PSU__DDRC__VENDOR_PART HYNIX [get_bd_cells /zynq_ultra_ps_e_0]
|Configurations Affected||All PS LPDDR4|
|Resolution||Vivado 2019.2 and later versions will always set the WDQS setting when LPDDR4 is used, regardless of this parameter.|