We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 72582

UltraScale Memory IP - Space Grade Kintex UltraScale XQRKU060 Device Byte Planner Errors or MIG 66-99 Error in Bank 46 or Bank 25


Version Found: DDR4 v2.2 (Rev. 7) and DDR3 v1.4 (Rev. 7)

Version Resolved: See (Xilinx Answer 58435)

Currently in Vivado 2019.1 there are restrictions on placing memory interfaces in Bank 46 or Bank 25 of the Space Grade Kintex UltraScale XQRKU060 device.  

Depending on your flow you will either encounter an "Unable to place ports" error with the Byte Planner tool or with a fixed pinout you will see the following error at implementation:

[Mig 66-99] Memory Core Error - [path_to_ip_instance] MIG restricts the usage of banks(25,46) for this device, as they have few unbonded pins. Please select some other banks or contact Technical Support

The tools are preventing any memory interface signals from being be assigned to any of the available bytes of Bank 46 or Bank 25.

In Bank 46 Byte 2, the N7 (A38) and N9 (B39) sites are not bonded out. In Bank 25 Byte 1, site N3 (AV39) is not bonded out.  

The restriction is due to the MIG tool and assumptions it makes about the site availability within Select I/O Bytes and how it handles assignment when generating the PHY.

Currently the work-around is to apply the tactical patch attached to this Answer Record.


In order to generate a memory interface which uses Bytes within Bank 46 or Bank 25 targeting the Space Grade Kintex UltraScale XQRKU060 Device, please apply the tactical patch attached to this Answer Record to your Vivado installation.

Additionally, when starting your Vivado session enter the following command in the Tcl console to ignore the DRC warnings generated by using Bank 46 or Bank 25:

set_param memory.ignoreSpecialBankRules true

After applying the patch and setting the parameter to ignore the Bank 46 and Bank 25 DRC checks you will be able to generate a valid memory interface. 


Do not assign any memory interface signals to Bank 46 Byte 2, or Bank 25 Byte 1.

Revision History:

08/27/2019 - Initial Release


文件名 文件大小 File Type
AR72582_vivado_2019_1_preliminary_rev2.zip 17 MB ZIP



Answer Number 问答标题 问题版本 已解决问题的版本
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 72582
日期 09/02/2019
状态 Active
Type 已知问题
IP More Less