AR# 72601


Vivado 2019.1 - compile_simlib fails for the IP "hdmi_gt_controller_v1_0_0" targetting VCS-MX


When I run compile_simlib to compile Vivado simulation libraries for VCS-MX, it fails for the hdmi_gt_controller_v1_0_0 IP.

The error message is as follows.

Error-[ITSFM] Illegal `timescale for module
/vivado/data/ip/xilinx/hdmi_gt_controller_v1_0/hdl/src/verilog/, 19
Module "hdmi_gt_controller_v1_0_0_lib_rst_v1_0" has `timescale but previous
module(s)/package(s) do not.
Please refer LRM 1364-2001 section 19.8.


This is a known issue that only happens when compiling with VCS-MX. 

It will be fixed in the 2019.2 IP sources.

To work around this issue, add the timescale (for example, timescale 1ns/1ps) to the following file:

<Vivado Install Area>/data/ip/xilinx/hdmi_gt_controller_v1_0/hdl/src/verilog/

AR# 72601
日期 07/30/2019
状态 Active
Type 已知问题
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