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AR# 72607

Virtex UltraScale+ HBM Controller - Debug Hub Clock Sometimes Not Connected which Results in Error at Implementation or Not Enabled Status in Hardware Manager

描述

Version Found: HBM v1.0 (Rev. 3)

Version Resolved: (Xilinx Answer 69267)

Depending on the specifics of the design flow or if design entry is done through IP Integrator, there can be cases when the tools have difficulty handling connection automation for the Debug Hub.

In these cases the tools might not be able to identify a clock source for the Debug Hub and the following error message will be seen at implementation:

ERROR: [Chipscope 16-213] The debug port 'dbg_hub/clk' has 1 unconnected channels (bits). This will cause errors during implementation.

In these scenarios if the bitstream is loaded to the FPGA then the HBM IP core will show "Calibration Status: Not Enabled".




解决方案

The work-around for this behavior is to manually connect the Debug Hub clock pin to a valid clock source. 

This can be done by adding a constraint similar to the example below to the design:

set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets */APB_0_PCLK]

This is a known issue with the HBM IP in both Vivado 2019.1 (HBM v1.0 Rev. 3) and Vivado 2019.2 (HBM v1.0 Rev. 4) .

Revision History:

08/09/2019 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
69267 Virtex UltraScale+ HBM Controller - Release Notes and Known Issues N/A N/A
AR# 72607
日期 08/09/2019
状态 Active
Type 已知问题
器件
Tools
IP
的页面