Version Found: HBM v1.0 (Rev. 3)
Version Resolved: (Xilinx Answer 69267)
Depending on the specifics of the design flow or if design entry is done through IP Integrator, there can be cases when the tools have difficulty handling connection automation for the Debug Hub.
In these cases the tools might not be able to identify a clock source for the Debug Hub and the following error message will be seen at implementation:
In these scenarios if the bitstream is loaded to the FPGA then the HBM IP core will show "Calibration Status: Not Enabled".
The work-around for this behavior is to manually connect the Debug Hub clock pin to a valid clock source.
This can be done by adding a constraint similar to the example below to the design:
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets */APB_0_PCLK]
This is a known issue with the HBM IP in both Vivado 2019.1 (HBM v1.0 Rev. 3) and Vivado 2019.2 (HBM v1.0 Rev. 4) .
08/09/2019 - Initial Release