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AR# 7262

FPGA Express: Is there an option to disable carry logic?

Description

Keywords: FPGA Express, Foundation, VHDL, Verilog, carry, arithmetic

Urgency: Standard

General Description:
Is there an option to disable carry logic when synthesizing HDL for XC4000, Spartan
and Virtex architectures?

解决方案

There is no way to disable the inference of carry logic when synthesizing arithmetic
functions using FPGA Express. As long as arithmetic operators are used in your HDL
code, carry logic will be inferred.
AR# 7262
创建日期 08/31/2007
Last Updated 10/03/2008
状态 Archive
Type 综合文章