AR# 72655


AXI Bridge for PCI Express - Max Link Width and Speed support for XC7Z012S devices


In the change log for the AXI Bridge for PCI Express IP, it states that Gen2x2 is supported with XC7Z012S devices. 

However, Vivado returns an error when implementing the generated IP for Gen2x2 configuration.

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express


There is a typo in the change log. The supported max width and link speed is Gen1x2 only.

This limitation for max link width and speed only applies to the AXI-PCIe Gen2 IP core. 

This device has Gen2x4 support with the Integrated Block for PCIe IP cores.

Revision History:

08/22/2019 - Initial Release

AR# 72655
日期 08/22/2019
状态 Active
Type 综合文章
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