How should a mixed voltage JTAG chain be laid out? What should the device order be, and what should the VCC of the parallel cable be?
NOTE: Although the following example uses 9500 CPLDs, this information also applies to FPGAs.
Example: A chain consists of 9500 (5V) and 9500XL (3.3V):
All Xilinx XL parts are 5V tolerant (unless otherwise selected), and the 5V parts (i.e., 9500 or 4000E) will recognize 3.3V as a valid high. Therefore, in this configuration, the chain order is not important (that is, it can either be 9500 -> 9500XL or 9500XL -> 9500).
The VCC connected to the parallel cable can be either 5V or 3.3V; however, we recommend that the cable be driven with the same voltage as the last device in the chain.
(NOTE: Although the following example uses 9500 CPLDs, this information
also applies to FPGAs.)
A chain consists of 5V, 3.3V, and 2.5V parts.
In this configuration, order is important. The 9500XV is 3.3V compatible, but not 5V
compatible. Therefore, the 9500 (operating at 5V) cannot be directly connected to the
9500XV. This connection can be completed if the VCC of the 9500 is set to 3.3V, or if there
is a 9500XL in between the two devices.
In either case, the VCC of the cable will need to be 3.3V (more robust) or 2.5V. Additionally,
if there is a 9500XL in the chain, we recommend that the devices descend in order such that
the lowest-voltage device is last in the chain:
9500 -> 9500XL -> 9500XV
(Use a VCC to the cable of 3.3V.)