AR# 7271


FPGA/Design Compiler: Can't make an adder in Synopsys bigger than 48-bits


Keywords: Synopsys, libraries, 4000xv, add, designware

Urgency: Standard

General Description:
When trying to infer an adder bigger than 48 bits in Synopsys Design Compiler or FPGA Compiler,
the following warning occurs during compile, and the adder is completely removed:

Warning: Synthetic library implementation 'xhm' in module 'add_sub_tc' is an empty netlist. (SYNH-9)


This problem is due to a size limitation of the designware libraries for the xc4000 series devices.

The only workaround for these large adders is to break up the large adder into smaller ones
or use Logiblox for Coregen to generate the larger adders and use these adders in your design.

Partitioning into smaller adders:

This can be easily done by adding the bottom bits and then adding the upper bits using the
carry out of the lower bits.

For example, if you are using a 64 bit adder you will need to do something like the following:

VHDL example:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity cnttest is
port (a: in STD_LOGIC_VECTOR (63 downto 0);
b: in STD_LOGIC_VECTOR (63 downto 0);
c: out STD_LOGIC_VECTOR (63 downto 0);
clk: in std_logic);
end cnttest;

architecture cnttest_arch of cnttest is

signal d,e : std_logic_vector(32 downto 0);
signal f,g : std_logic_vector(31 downto 0);
signal temp,temp2 : std_logic_vector (32 downto 0);


d(31 downto 0) <= a(63 downto 32);
e(31 downto 0) <= a (31 downto 0);
f <= b(63 downto 32);
g <= b(31 downto 0);

temp <= (e + g); -- add the lower bits
temp2 <=(f & temp(32)) + (g & temp(32)); -- concat the carry out of lower bits to upper bits and add

c(31 downto 0) <= temp(31 downto 0);
c(63 downto 32) <= temp2(32 downto 1);

end cnttest_arch;


In the above example the bottom 32 bits are extended to 33 so that the carry out can be used
in the add of the upper bits.
AR# 7271
日期 08/31/2001
状态 Archive
Type 综合文章
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