AR# 72780

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2019.1 - Versal IP example designs fail during elaboration when running post-synthesis functional simulation targeting VCS

描述

Versal IP example designs fail during the elaboration phase at the post synthesis level when launching simulation with VCS.

解决方案

This issue occurs in Versal IP example designs because the tool generated elaborate.sh is missing "-liblist unisim" with the vcs command.

As a work-around, please use the following setting before launching simulation.

set_property -name {vcs.elaborate.vcs.more_options} -value {-liblist unisim} -objects [get_filesets sim_1]
AR# 72780
日期 11/08/2019
状态 Active
Type 综合文章
器件
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