AR# 72789


UltraScale/UltraScale+ DDR3/DDR4 IP - Usage Guidelines for Multiple High Frequency Save/Restore Cycles


Version Found: DDR4 2016.3 v2.1 and DDR3 2016.3 v1.3

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

The purpose of this Answer Record is to provide usage guidelines when performing multiple calibration data save/restore cycles over a short period of time.

When performing hundreds of calibration data save/restore cycles over a short period of time it's possible data errors will occur after restoration.

This is due to an accumulation of rounding computations in the calibration data which can result in a suboptimal operating point after restoration.


To avoid the potential for post restoration data errors it is recommended to use the original calibration results saved after the first power-on reset of the FPGA instead of saving new calibration data prior to entering self-refresh.

Using the original calibration data in these scenarios will ensure that the restoration data returns the memory interface to a valid operating point.

Any changes in temperature or voltage are automatically handled by DCI calibration in the PHY, as well as the DQS Gate calibration stage which will occur before resuming normal operation.

Continue to use the original calibration data until the FPGA is powered off and then save the new calibration results upon the next full power-on and FPGA configuration cycle.

Revision History

10/14/2019 - Initial Release



Answer Number 问答标题 问题版本 已解决问题的版本
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
AR# 72789
日期 10/14/2019
状态 Active
Type 已知问题
器件 More Less
People Also Viewed