AR# 73044

UHD SDI GT v2.0 - Why Does the UHD-SDI GT IP fail Synthesis operation in Vivado 2019.1 for -1LV UltraScale, UltraScale+ and Zynq MPSoC Devices

描述

In a design targeting a 1LV UltraScale, UltraScale+, or Zynq MPSoC Device which includes the UHD-SDI GT IP, I get the following errors when running synthesis:

ERROR: [IP_Flow 19-3477] Update of parameter 'PARAM_VALUE.TX_REFCLK_FREQUENCY' failed for IP 'test_uhdsdi_gt_0_0/uhdsdi_gtwiz_gthe4'. No valid values found for TX_REFCLK_FREQUENCY, see other error messages to determine IP configuration problemsERROR: [IP_Flow 19-3461] Value '40' is out of the range for parameter 'Internal data width(RX_INT_DATA_WIDTH)' for IP 'test_uhdsdi_gt_0_0/uhdsdi_gtwiz_gthe4' . Valid values are - 0ERROR: [IP_Flow 19-3461] Value '40' is out of the range for parameter 'Internal data width(TX_INT_DATA_WIDTH)' for IP 'test_uhdsdi_gt_0_0/uhdsdi_gtwiz_gthe4' . Valid values are - 0ERROR: [IP_Flow 19-3488] Validation failed for parameter 'Line rate (Gb/s)(RX_LINE_RATE)' for IP 'test_uhdsdi_gt_0_0/uhdsdi_gtwiz_gthe4'. Value '11.88' is out of the range (0.5,10.3125)ERROR: [IP_Flow 19-3488] Validation failed for parameter 'Line rate (Gb/s)(TX_LINE_RATE)' for IP 'test_uhdsdi_gt_0_0/uhdsdi_gtwiz_gthe4'. Value '11.88' is out of the range (0.5,10.3125)ERROR: [IP_Flow 19-3461] Value '148.5' is out of the range for parameter 'Actual Reference clock (MHz)(RX_REFCLK_FREQUENCY)' for IP 'test_uhdsdi_gt_0_0/uhdsdi_gtwiz_gthe4' . Valid values are - 64.453125, 64.8584906, 65.2689873, ..., 814.1447368ERROR: [Common 17-39] 'set_property' failed due to earlier errors.CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado_2019.1/Vivado/2019.1/data/ip/xilinx/uhdsdi_gt_v2_0/elaborate/elaborate_usplus.xit': ERROR: [Common 17-39] 'set_property' failed due to earlier errors. ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).ERROR: [IP_Flow 19-3541] IP Elaboration error: Failed to generate IP 'uhdsdi_gt_0'. Failed to generate 'Elaborate Sub-Cores' outputs: create_bd_cell: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5707.656 ; gain = 0.000ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

Why do I get this error?

解决方案

The UHD-SDI GT IP v2.0 which was deployed in Vivado 2019.1 has a default line rate of 11.88Gbps, which is not supported for -1LV devices.

As a result you will observe these errors when performing synthesis on the UHD-SDI GT IP in Vivado 2019.1.

In the 2019.2 version and later, the UHD SDI-GT will have an updated GUI with a new parameter called LINE RATE for the user to select the desired line rate.

Also, for -1LV devices, the default line rate has been set to 5.94 Gbps, and for the other high power devices a line rate of 11.88Gbps can be selected.

Users encountering these errors should update to Vivado 2019.2 or later.

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AR# 73044
日期 11/27/2019
状态 Active
Type 已知问题
器件 More Less
Tools More Less
IP