When implementing a design that includes a DDR4 IP core targeting an UltraScale/UltraScale+ device, the following errors can occur:
These errors are very rare and are due to an issue synthesizing certain mux conditions within the IP.
When targeting Vivado 2019.2, the errors can be resolved by applying the two patches attached to this Answer Record. Please download the patches and review the included installation instructions.
This issue is resolved starting with Vivado 2019.2.1 where the patch is no longer required.
Users who encounter this issue must either update to Vivado 2019.2 and install the patch or use Vivado 2019.2.1 or newer.
11/12/2019 - Initial Release