AR# 73127

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2019.1 - LogiCORE I2S Receiver v1.0 (Rev 3) and LogiCORE I2S Transmitter v1.0 (Rev 3) - Can I configure a 32-bit data period in the I2S Transmitter/ Receiver IP?

描述

(PG308) lists support for 16/24-bit data (LR Clock Period). 

Many IC's are available with 32-bit data. 

Can the I2S IP cores capture/send a 32-bit data word?


解决方案

This feature enhancement is targeted for Vivado 2020.1 and later versions.

Versions prior to Vivado 2020.1 are addressed below.








链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
70288 LogiCORE I2S Receiver - Release Notes and Known Issues for the Vivado 2018.1 tool and later versions N/A N/A

相关答复记录

AR# 73127
日期 01/06/2020
状态 Active
Type 综合文章
IP
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