AR# 73173

UHD-SDI GT v2.0 (Rev 1) - Patch Update for UHD-SDI GT in Vivado 2019.2

描述

This answer record contains patch updates for the LogiCORE UHD-SDI GT v2.0 (Rev 1) in Vivado 2019.2.

解决方案

Fixes:

This patch fixes an issue with the LogiCORE UHD-SDI GT v2.0 (Rev 1) in the Vivado 2019.2 design tools.


Patch Rev 2:

(Xilinx Answer 73527) Why do I have synthesis issues when selecting the CPLL in Vivado 2019.2?

Patch Rev 1:

(Xilinx Answer 73174)Switching between PICXO and FRACXO has no impact on the ports of the core in Vivado 2019.2
(Xilinx Answer 73203) Why do I receive a Synthesis error when enabling 4 lanes in Vivado 2019.2?
(Xilinx Answer 73216) Why does synthesis fails in Vivado 2019.2 when the core is configured for HD-SDI, 3G-SDI or 6G-SDI?

See the individual Answer Records for details on which release they are fixed in.

Note: This patch will not be needed with Vivado 2020.1 and later versions.

Patch Installation:

Install the patch as per the instructions in the included README.txt file to resolve this issue.

附件

文件名 文件大小 File Type
AR73173_Vivado_2019_2_preliminary_rev2.zip 224 KB ZIP

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AR# 73173
日期 03/27/2020
状态 Active
Type 已知问题
IP