2. 技术支持
  3. AR# 7320:
  4. AR# 73203: UHD-SDI GT v2.0 - Why do I receive a Synthesis error when enabling 4 lanes in Vivado 2019.2?

AR# 73203

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UHD-SDI GT v2.0 - Why do I receive a Synthesis error when enabling 4 lanes in Vivado 2019.2?

描述

When synthesizing a design including the UHD-SDI GT IP with 4 lanes enabled in Vivado 2019.2, the following error is seen:

[Synth 8-448] named port connection 'intf_0_gt_common_sdm0data_in' does not exist for instance 'inst' of module '<modulename>' [<module name_uhdsdi_gt_0_0.v 485>]

image-2019-11-20-14-56-18-114.png




解决方案

This is a known issue for the UHD-SDI GT in Vivado 2019.2, where enabling 4 lanes causes a synthesis error.

  • 2019.2 - Users can download the latest UHD-SDI GT Patch from (Xilinx Answer 73173) to work around this issue.

This issue will be fixed in a future version.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
68766 SMPTE UHD-SDI RX Subsystem - Release Notes and Known Issues for the Vivado 2017.3 tool and later versions N/A N/A
68767 SMPTE UHD-SDI Transmitter Subsystem - Release Notes and Known Issues for the Vivado 2017.3 tool and later versions N/A N/A
70291 LogiCORE UHD-SDI GT - Release Notes and Known Issues for the Vivado 2017.3 tool and later versions N/A N/A
AR# 73203
日期 12/11/2019
状态 Active
Type 综合文章
IP
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