AR# 73417


PCI Express Integrated Block (Vivado 2019.2) - CPLL fails to lock in when reference clock is set to 250MHz at Gen1 rate


When the IP cores listed below are configured with the following options, CPLL fails to clock:

  • Maximum link speed: 2.5Gbps
  • Reference clock frequency: 250MHz
  • GT DRP clock selection: Internal

The following IP cores are affected:

  • UltraScale+ PCI Express Integrated Block
  • UltraScale+ PCI Express 4c Integrated Block
  • DMA Subsystem for PCI Express
  • Queue DMA subsystem for PCI Express

本文是 PCI Express 解决方案中心的一部分

(赛灵思答复记录 34536)面向 PCI Express 的赛灵思解决方案中心


This a known issue to be fixed in a future version of the core.


Please install the patches for your corresponding version of Vivado.





  • 2020 年 3 月 26 日 - 初始版本
  • 06/13/2020 - Patch Update (Rev2)


文件名 文件大小 File Type 22 MB ZIP
AR# 73417
日期 06/27/2020
状态 活跃
Type 一般类
器件 More Less
IP More Less
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