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AR# 7354

3.1i Timing Analyzer - Virtex-II - Advaned Analysis coverage is different than expected for SRLC16.

Description

keywords: advanced, analysis, SRLC16, coverage

General Description:

During Advanced Analysis, the percent coverage is

different than expected for SRLC16.

Also See (Xilinx Solution 6321) & (Xilinx Solutoin 2963)

解决方案

The shift registers are being packed correctly into

both LUTs of the Slices. The real problem is that

the speed files are missing setup/hold times from

the Address to the Clock. Normally there is no

setup time for the Address lines, since they are

considered a data path. In this case, there

should be setup/hold times available.

This issue will be address in a future release.

AR# 7354
创建日期 08/31/2007
Last Updated 01/18/2010
状态 Archive
Type 综合文章