描述

If the input to the CLKDLL is less than 25 MHz, will the CLKDLL lock? What will the outputs of the CLKDLL look like?

解决方案

If the input frequency of the CLKDLL is less than 25 MHz, the CLKDLL will not lock. The CLKDLL will not lock because the input clock frequency is below the required minimum input clock frequency (CLKINLF). The CLKDLL will continuously try to achieve lock on the CLKIN signal, and the output will slew in phase, period, and duty cycle as the control logic attempts to lock on the input clock.

For more information on the CLKDLL specifications, please see the DLL timing parameters in the "Virtex 2.5 V FPGA DC and Switching Characteristics" data sheet located at:

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