The PCI master may stop bursting data after two PCI clocks, even though I wish to transfer multiple DWORDS during simulation. Why does this occur?
The length of the burst is controlled by the Latency Timer in the PCI configuration header. In a real PCI system, this value is set by the OS. However, during simulation, you must set this value by using a command such as the WRITE_CONFIG command provided with the test bench.
You will have to modify the stimulus.v/vhd files to set the Latency Timer. Adding a WRITE_CONFIG statement as shown below will set the Latency Timer to the maximum value.
-- setup MLT to maximum value
WRITE_CONFIG( X"0000000C", X"0000ff00");
Note that this statement will also attempt to write to the BIST, Header Type, and Cache Line Size registers in the configuration header. However, these registers are hard-coded in the LogiCORE PCI Interface and cannot be set/reset with a CONFIG_WRITE command. You should experiment with the Latency Timer value to get an optimum result.