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AR# 7419

Virtex - How do I set the CLKDV_DIVIDE property for the CLKDLL?

Description

The CLKDV output of a CLKDLL can take a divisor of 1.5, 2, 2.5, 3, 4, 5, 8, or 16. The default is 2. In order to change the value, you must change the CLKDV_DIVIDE property to a new value.

解决方案

To do this, you can add the following syntax to the UCF: 

 

INST <CLKDLL_name> clkdv_divide = N; 

 

(Where N = the divisor value and <CLKDLL_name> is the instance name.)

 

VHDL 

 

It is also possible to place the CLKDV_DIVIDE attribute in the VHDL code if the synthesis tool allows attribute passing. The following illustrates the general syntax for this. 

 

Place the following in the architecture before the "begin" keyword: 

 

attribute <name> : string; 

attribute <name> of <instance> : label is <value>; 

 

Example VHDL code portion: 

 

attribute CLKDV_DIVIDE: string; 

attribute CLKDV_DIVIDE of U1: label is "1.5"; 

 

begin 

U1 : CLKDLL port map( 

CLKIN => CLK, 

RST => RST, 

CLKFB => CLKFB, 

CLK0 => a, 

CLK90 => b, 

CLK180 => c, 

CLK270 => d, 

CLKDV => e, 

CLK2x => f, 

LOCKED => lock);

 

Verilog 

 

It is also possible to place the CLKDV_DIVIDE attribute in the Verilog code if the synthesis tool allows attribute passing. The following illustrates the general syntax for this. (The example shown is for Synopsys; if you are using another synthesis tool, use the proper syntax for attribute passing in that tool): 

 

//synopsys attribute <name> <value> 

 

This comment is placed immediately after the instantiated component. 

 

Example Verilog code portion: 

 

CLKDLL U1 (.CLKIN(CLK), .CLKFB(CLKFB), .RST(RST), 

.CLK0(a), .CLK90(b), .CLK180(c), .CLK270(d), 

.CLK2X(e), .CLKDV(f), .LOCKED(lock)); 

/* synopsys attribute 

CLKDV_DIVIDE "1.5" 

*/

AR# 7419
创建日期 08/21/2007
Last Updated 05/14/2014
状态 Archive
Type 综合文章