AR# 7497


FPGA Express 3.3: Express inverting load/clock signal for 4000/Spartan input latches


Keywords : Foundation, FPGA, Express, latch, invert, 4000, Spartan, 4000XL, SpartanXL

Urgency : Standard

General Description:
FPGA Express 3.x incorrectly inverts all load (G input) signals for inferred ILD latches.

This happens when targeting all FPGA devices except for Virtex. When examining the XNF file you
will see a ", INV" on the G pin of the ILD component.


Several workarounds are available:

-- Instantiate the ILD component
-- Invert the Gate signal before latches that are moved into the IOB
-- Disable the I/O Register Merge feature in the Express Constraints Editor
-- Use registers instead of latches
AR# 7497
日期 08/30/2001
状态 Archive
Type 综合文章
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