AR# 7504: CPLD, CoolRunner-II/XPLA3 - How do I make my design fit into the selected device?
CPLD, CoolRunner-II/XPLA3 - How do I make my design fit into the selected device?
My design does not fit into the selected device. How can I make it fit?
The following suggestions can help make a design fit into a selected device. If at all possible, you might consider a larger device, particularly if the following suggestions do not work.
You must first determine why the design demands more resources than the selected device allows. The error message you receive might help. For example, if it reports, "Design exceeds maximum number of nodes", you can use the number that follows to determine how many macrocells the design requires for the current fitter settings. If the error message says, "Unable to fit design", more investigation is required.
Targeting the next larger device can help determine the resources required. If the design fits into the next larger device, look at the fitter report ("*.rpt" file). The top portion of the file shows the resources used. If you keep in mind the resources that are available for the smaller device, you can often get an idea of the location of the limiting item.
If clocks, asynchronous resets/presets, or output enables are the limiting items, you might be able to fit the design by reducing the amounts of these particular resources. For example, if asynchronous resets are the limiting item, convert them to synchronous resets. If it is not possible to remove any of these items from your design, you must use the next larger device.
If product terms are the limiting items, it might be possible to fit the design by adjusting the "Collapsing PTerm Limit" setting in the Fit -> Properties -> Advanced window. Using a smaller number on this setting will create more nodes, thereby reducing the number of product terms utilized in the logic block. This is indicated by fewer product terms being used in the PLA. However, this also reduces the maximum speed at which the part can operate, because the number of logic levels is increased.
If macrocells are an issue, raising the number on the "Max P-Terms Per Equation" setting will reduce the number of macrocells used. However, this can cause product terms to become a limiting item because more of the PLA, which is limited in size, may be used.
The Block Input Limit allows you to specify the maximum permissible fan-in per function block for synthesis and fitting. Generally, you should leave this value set to the default (38), as it allows for high fan-in while allowing some inputs to be set aside for future design changes. This value can be increased; however, raising this value above the default value will greatly reduce the ability of your design to fit with changes while retaining a fixed pin-out.
For more information, see (Xilinx XAPP444): "CPLD Fitting Tips and Tricks."