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2.1i COREGEN: Missing MIF file for Virtex Single and Dual Port Block RAM modules
Keywords: mif, core, vhdl, verilog
The MIF file for the BlockRAM modules in the 2.1i release do not
appear to be generated even when the "Write MIF" checkbox is
This is a new problem found in the 2.1i release. The MIF file is
written to the same directory where the coregen.log file is
On PCs: coregen.log and any MIF files are written to $XILINX\coregen\tmp
On Workstations: coregen.log and any MIF files are written to the
directory from which you invoke the CORE Generator.